The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased. As lithographic features are reduced, for example, to below 40 nanometers (nm), high numerical aperture processes are needed to overcome the resolution limit. The use of a trilayer photoresist films scheme appears to be promising in this regard. Specifically trilayer photoresist films can provide for improvements in line edge roughness (LER) and line width roughness (LWR) among other benefits.
Using trilayer schemes however raises challenges, especially with the decreasing technology nodes and pitch provided between features. The decreasing feature size and pitch can lead to collapse of photoresist features. This can collapse or pattern peeling may be due to the deterioration of adhesion between the top photoresist layer and the middle layer of the trilayer scheme. Thus, a process and material that reduces, minimizes or removes problems with a patterning material is desired.